On Thu, Jan 07, 2021 at 11:12:16AM +0100, Marek Vasut wrote:
> The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words
> after the descriptor. Use this to pad the descriptors to cacheline size and
> remove the need for noncached memory altogether. Moreover, this lets Tegra
>
Hi Marek
On 1/7/21 7:16 PM, Marek Vasut wrote:
> On 1/7/21 5:33 PM, Stephen Warren wrote:
>> On 1/7/21 3:12 AM, Marek Vasut wrote:
>>> The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words
>>> after the descriptor. Use this to pad the descriptors to cacheline size and
>>>
On 1/7/21 5:33 PM, Stephen Warren wrote:
On 1/7/21 3:12 AM, Marek Vasut wrote:
The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words
after the descriptor. Use this to pad the descriptors to cacheline size and
remove the need for noncached memory altogether. Moreover, this
On 1/7/21 3:12 AM, Marek Vasut wrote:
> The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words
> after the descriptor. Use this to pad the descriptors to cacheline size and
> remove the need for noncached memory altogether. Moreover, this lets Tegra
> use the generic cache
The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words
after the descriptor. Use this to pad the descriptors to cacheline size and
remove the need for noncached memory altogether. Moreover, this lets Tegra
use the generic cache flush / invalidate operations.
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