On Monday 13 December 2021 08:36:00 Stefan Roese wrote:
> Hi Pali,
>
> On 12/10/21 15:23, Pali Rohár wrote:
>
>
>
> > > > > So I think the correct behavior should be:
> > > > >
> > > > > 1. pci-mvebu.c configures all controller registers to correct values
> > > > > 2. PCIe port is enabled via
Hi Pali,
On 12/10/21 15:23, Pali Rohár wrote:
So I think the correct behavior should be:
1. pci-mvebu.c configures all controller registers to correct values
2. PCIe port is enabled via SoC-specific register
3. pci-mvebu.c waits for link up
I guess that reset-controller does not help, as
On Monday 29 November 2021 17:07:54 Stefan Roese wrote:
> On 11/29/21 15:28, Pali Rohár wrote:
> > On Monday 29 November 2021 14:27:48 Pali Rohár wrote:
> > > On Monday 29 November 2021 13:30:45 Stefan Roese wrote:
> > > > Hi Pali,
> > > >
> > > > On 11/29/21 12:47, Pali Rohár wrote:
> > > > >
On Monday 29 November 2021 18:09:22 Marek Behún wrote:
> On Mon, 29 Nov 2021 17:07:54 +0100
> Stefan Roese wrote:
>
> > > Just I'm not sure if this "enable port functionality" should be
> > > implemented via Reset Controller API...
> >
> > How else should / could this be done then? Do you
On Mon, 29 Nov 2021 17:07:54 +0100
Stefan Roese wrote:
> > Just I'm not sure if this "enable port functionality" should be
> > implemented via Reset Controller API...
>
> How else should / could this be done then? Do you have alterative ideas?
syscon regmap
On 11/29/21 15:28, Pali Rohár wrote:
On Monday 29 November 2021 14:27:48 Pali Rohár wrote:
On Monday 29 November 2021 13:30:45 Stefan Roese wrote:
Hi Pali,
On 11/29/21 12:47, Pali Rohár wrote:
Hello!
On Monday 29 November 2021 10:22:58 Stefan Roese wrote:
On 11/29/21 10:06, Pali Rohár
On Monday 29 November 2021 14:27:48 Pali Rohár wrote:
> On Monday 29 November 2021 13:30:45 Stefan Roese wrote:
> > Hi Pali,
> >
> > On 11/29/21 12:47, Pali Rohár wrote:
> > > Hello!
> > >
> > > On Monday 29 November 2021 10:22:58 Stefan Roese wrote:
> > > > On 11/29/21 10:06, Pali Rohár wrote:
On Monday 29 November 2021 13:30:45 Stefan Roese wrote:
> Hi Pali,
>
> On 11/29/21 12:47, Pali Rohár wrote:
> > Hello!
> >
> > On Monday 29 November 2021 10:22:58 Stefan Roese wrote:
> > > On 11/29/21 10:06, Pali Rohár wrote:
> > >
> > >
> > >
> > > > > > After this DTS change, pci-mvebu.c
Hi Pali,
On 11/29/21 12:47, Pali Rohár wrote:
Hello!
On Monday 29 November 2021 10:22:58 Stefan Roese wrote:
On 11/29/21 10:06, Pali Rohár wrote:
After this DTS change, pci-mvebu.c will just replace value of current
number of lanes (which is set to 4 by serdes code) to value from DTS,
Hello!
On Monday 29 November 2021 10:22:58 Stefan Roese wrote:
> On 11/29/21 10:06, Pali Rohár wrote:
>
>
>
> > > > After this DTS change, pci-mvebu.c will just replace value of current
> > > > number of lanes (which is set to 4 by serdes code) to value from DTS,
> > > > which is 4. Therefore
On 11/29/21 10:06, Pali Rohár wrote:
After this DTS change, pci-mvebu.c will just replace value of current
number of lanes (which is set to 4 by serdes code) to value from DTS,
which is 4. Therefore there should be no change.
Could you test whole patch series with above DTS change if it
On Monday 29 November 2021 08:46:47 Stefan Roese wrote:
> Hi Pali,
>
> On 11/23/21 16:59, Pali Rohár wrote:
> > On Friday 19 November 2021 07:55:00 Stefan Roese wrote:
> > > On 11/18/21 19:01, Pali Rohár wrote:
> > > > On Friday 12 November 2021 15:01:57 Stefan Roese wrote:
> > > > > On 11/11/21
Hi Pali,
On 11/23/21 16:59, Pali Rohár wrote:
On Friday 19 November 2021 07:55:00 Stefan Roese wrote:
On 11/18/21 19:01, Pali Rohár wrote:
On Friday 12 November 2021 15:01:57 Stefan Roese wrote:
On 11/11/21 16:35, Marek Behún wrote:
From: Pali Rohár
As explained in commit 3bedbcc3aa18
On Friday 19 November 2021 07:55:00 Stefan Roese wrote:
> On 11/18/21 19:01, Pali Rohár wrote:
> > On Friday 12 November 2021 15:01:57 Stefan Roese wrote:
> > > On 11/11/21 16:35, Marek Behún wrote:
> > > > From: Pali Rohár
> > > >
> > > > As explained in commit 3bedbcc3aa18 ("arm: mvebu: a38x:
On 11/18/21 19:01, Pali Rohár wrote:
On Friday 12 November 2021 15:01:57 Stefan Roese wrote:
On 11/11/21 16:35, Marek Behún wrote:
From: Pali Rohár
As explained in commit 3bedbcc3aa18 ("arm: mvebu: a38x: serdes: Don't
overwrite read-only SAR PCIe registers") it is required to set Maximum
On Friday 12 November 2021 15:01:57 Stefan Roese wrote:
> On 11/11/21 16:35, Marek Behún wrote:
> > From: Pali Rohár
> >
> > As explained in commit 3bedbcc3aa18 ("arm: mvebu: a38x: serdes: Don't
> > overwrite read-only SAR PCIe registers") it is required to set Maximum Link
> > Width bits of
On 11/11/21 16:35, Marek Behún wrote:
From: Pali Rohár
As explained in commit 3bedbcc3aa18 ("arm: mvebu: a38x: serdes: Don't
overwrite read-only SAR PCIe registers") it is required to set Maximum Link
Width bits of PCIe Root Port Link Capabilities Register depending of number
of used serdes
From: Pali Rohár
As explained in commit 3bedbcc3aa18 ("arm: mvebu: a38x: serdes: Don't
overwrite read-only SAR PCIe registers") it is required to set Maximum Link
Width bits of PCIe Root Port Link Capabilities Register depending of number
of used serdes lanes. As this register is part of PCIe
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