Re: [PATCH u-boot-marvell 1/5] serial: a37xx: Fix parent clock rate value and divider calculation

2021-05-27 Thread Stefan Roese
On 25.05.21 19:42, Marek Behún wrote: From: Pali Rohár UART parent clock is by default the platform's xtal clock, which is 25 MHz. The value defined in the driver, though, is 25.8048 MHz. This is a hack for the suboptimal divisor calculation Divisor = UART clock / (16 * baudrate) which

[PATCH u-boot-marvell 1/5] serial: a37xx: Fix parent clock rate value and divider calculation

2021-05-25 Thread Marek Behún
From: Pali Rohár UART parent clock is by default the platform's xtal clock, which is 25 MHz. The value defined in the driver, though, is 25.8048 MHz. This is a hack for the suboptimal divisor calculation Divisor = UART clock / (16 * baudrate) which does not use rounding division, resulting in