On 25.05.21 19:42, Marek Behún wrote:
From: Pali Rohár
UART parent clock is by default the platform's xtal clock, which is
25 MHz.
The value defined in the driver, though, is 25.8048 MHz. This is a hack
for the suboptimal divisor calculation
Divisor = UART clock / (16 * baudrate)
which
From: Pali Rohár
UART parent clock is by default the platform's xtal clock, which is
25 MHz.
The value defined in the driver, though, is 25.8048 MHz. This is a hack
for the suboptimal divisor calculation
Divisor = UART clock / (16 * baudrate)
which does not use rounding division, resulting in
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