According to the reference manual, the Reset Configuration
Word Low Register bits 2-3 must be set to 0b10.
Signed-off-by: Christophe Leroy <christophe.le...@csgroup.eu>
---
arch/powerpc/cpu/mpc83xx/hrcw/Kconfig | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
index b67ccd661d..44f66cd528 100644
--- a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
@@ -539,8 +539,7 @@ config DDR_MC_CLOCK_MODE
config SYSTEM_PLL_VCO_DIV
int
- default 0 if ARCH_MPC832X
- default 2 if ARCH_MPC8313
+ default 2 if ARCH_MPC8313 || ARCH_MPC832X
default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X
default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X
default 2 if SYSTEM_PLL_VCO_DIV_8 && !ARCH_MPC8360 && !ARCH_MPC837X
--
2.39.2
