Re: [PATCH v1 1/1] x86: tangier: Fix DMA controller IRQ polarity in CSRT

2021-07-30 Thread Bin Meng
Hi Simon, On Sat, Jul 31, 2021 at 9:03 AM Simon Glass wrote: > > On Fri, 30 Jul 2021 at 14:15, Andy Shevchenko > wrote: > > > > IRQ polarity in CSRT has the same definition as by ACPI specification > > chapter 19.6.64 "Interrupt (Interrupt Resource Descriptor Macro)", i.e. > > ActiveHigh is 0, a

Re: [PATCH v1 1/1] x86: tangier: Fix DMA controller IRQ polarity in CSRT

2021-07-30 Thread Simon Glass
On Fri, 30 Jul 2021 at 14:15, Andy Shevchenko wrote: > > IRQ polarity in CSRT has the same definition as by ACPI specification > chapter 19.6.64 "Interrupt (Interrupt Resource Descriptor Macro)", i.e. > ActiveHigh is 0, and ActiveLow is 1. On Intel Tangier the DMA controller > IRQ polarity is Acti

Re: [PATCH v1 1/1] x86: tangier: Fix DMA controller IRQ polarity in CSRT

2021-07-30 Thread Bin Meng
On Sat, Jul 31, 2021 at 7:44 AM Bin Meng wrote: > > On Sat, Jul 31, 2021 at 4:15 AM Andy Shevchenko > wrote: > > > > IRQ polarity in CSRT has the same definition as by ACPI specification > > chapter 19.6.64 "Interrupt (Interrupt Resource Descriptor Macro)", i.e. > > ActiveHigh is 0, and ActiveLow

Re: [PATCH v1 1/1] x86: tangier: Fix DMA controller IRQ polarity in CSRT

2021-07-30 Thread Bin Meng
On Sat, Jul 31, 2021 at 4:15 AM Andy Shevchenko wrote: > > IRQ polarity in CSRT has the same definition as by ACPI specification > chapter 19.6.64 "Interrupt (Interrupt Resource Descriptor Macro)", i.e. > ActiveHigh is 0, and ActiveLow is 1. On Intel Tangier the DMA controller > IRQ polarity is Ac

[PATCH v1 1/1] x86: tangier: Fix DMA controller IRQ polarity in CSRT

2021-07-30 Thread Andy Shevchenko
IRQ polarity in CSRT has the same definition as by ACPI specification chapter 19.6.64 "Interrupt (Interrupt Resource Descriptor Macro)", i.e. ActiveHigh is 0, and ActiveLow is 1. On Intel Tangier the DMA controller IRQ polarity is ActiveHigh. Note, in DSDT (see southcluster.asl) it's described cor