On 5/17/23 11:41 PM, Yanhong Wang wrote:
SPL runs on the L2 LIM, which is 2M in size mapped at 0x800.This
region consists of 16 0x2 sized regions, each one can be used as
either L2 cache way or SRAM (not both).From top to bottom, you have way
0-15.The way 0 is always enabled, so SPL can o
SPL runs on the L2 LIM, which is 2M in size mapped at 0x800.This
region consists of 16 0x2 sized regions, each one can be used as
either L2 cache way or SRAM (not both).From top to bottom, you have way
0-15.The way 0 is always enabled, so SPL can only use at most 0x1e
bytes of memory.So
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