Hello Conor,
On 26.10.22 09:49, Conor Dooley wrote:
> A late ack is currently being sent at the end of a transfer due to
> incorrect logic in mchp_corei2c_empty_rx(). Currently the Assert Ack
> bit is being written to the controller's control reg after the last
> byte has been received, causing
Hello Conor,
On 26.10.22 09:49, Conor Dooley wrote:
> A late ack is currently being sent at the end of a transfer due to
> incorrect logic in mchp_corei2c_empty_rx(). Currently the Assert Ack
> bit is being written to the controller's control reg after the last
> byte has been received, causing
Hi Conor,
> On Wed, 2022-10-26 at 07:54 +, Conor Dooley - M52691 wrote:
> On 26/10/2022 08:49, Conor Dooley wrote:
> > A late ack is currently being sent at the end of a transfer due to
> > incorrect logic in mchp_corei2c_empty_rx(). Currently the Assert
> > Ack
> > bit is being written to the
> On Wed, 2022-10-26 at 08:49 +0100, Conor Dooley wrote:
> A late ack is currently being sent at the end of a transfer due to
> incorrect logic in mchp_corei2c_empty_rx(). Currently the Assert Ack
> bit is being written to the controller's control reg after the last
> byte has been received,
On 26/10/2022 08:49, Conor Dooley wrote:
> A late ack is currently being sent at the end of a transfer due to
> incorrect logic in mchp_corei2c_empty_rx(). Currently the Assert Ack
> bit is being written to the controller's control reg after the last
> byte has been received, causing it to sent
A late ack is currently being sent at the end of a transfer due to
incorrect logic in mchp_corei2c_empty_rx(). Currently the Assert Ack
bit is being written to the controller's control reg after the last
byte has been received, causing it to sent another byte with the ack.
Instead, the AA flag
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