On Wed, Apr 6, 2022 at 9:03 PM Peng Fan (OSS) wrote:
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>
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> On 2022/4/1 22:30, Marek Vasut wrote:
> > Add clock tables required to bring up DWC3 USB, USB PHY and HSIOMIX domain.
> >
> > Signed-off-by: Marek Vasut
> > Cc: Fabio Estevam
> > Cc: Peng Fan
> > Cc: Stefano Babic
> > Cc: Ye Li
>
>
On 2022/4/1 22:30, Marek Vasut wrote:
Add clock tables required to bring up DWC3 USB, USB PHY and HSIOMIX domain.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
Cc: Ye Li
Reviewed-by: Peng Fan
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V2: - Get and probe 24m clock without registering it agai
Add clock tables required to bring up DWC3 USB, USB PHY and HSIOMIX domain.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
Cc: Ye Li
---
V2: - Get and probe 24m clock without registering it again (suggested by Ye)
- Add 32k clock the same way for usb_root_clk
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