On 21:23-20220311, Vignesh Raghavendra wrote:
> Patch 1 switches AM64 to use armv8 per-cpu timer at A53 SPL/U-Boot
> stage as done in other TI K3 platforms
>
> Patch 2 corrects DM timer freq to be 200MHz (used at R5 SPL stage)
>
> v2:
> Update commit message 1/2 as per Nishanth's suggestion
>
Patch 1 switches AM64 to use armv8 per-cpu timer at A53 SPL/U-Boot
stage as done in other TI K3 platforms
Patch 2 corrects DM timer freq to be 200MHz (used at R5 SPL stage)
v2:
Update commit message 1/2 as per Nishanth's suggestion
Reword commit msg in 2/2 to be more readable.
v1:
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