Re: [PATCH v2 03/22] clk: rockchip: rk3399: Improve support for SCLK_PCIEPHY_REF clock

Hi Jonas, On 5/6/24 5:17 PM, Jonas Karlman wrote: Hi Quentin, On 2024-05-06 13:07, Quentin Schulz wrote: Hi Jonas, On 5/1/24 6:22 PM, Jonas Karlman wrote: rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the SCLK_PCIEPHY_REF clock. The existing enable/disable ops for SCL

Re: [PATCH v2 03/22] clk: rockchip: rk3399: Improve support for SCLK_PCIEPHY_REF clock

Hi Quentin, On 2024-05-06 13:07, Quentin Schulz wrote: > Hi Jonas, > > On 5/1/24 6:22 PM, Jonas Karlman wrote: >> rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the >> SCLK_PCIEPHY_REF clock. >> >> The existing enable/disable ops for SCLK_PCIEPHY_REF currently force >> use o

Re: [PATCH v2 03/22] clk: rockchip: rk3399: Improve support for SCLK_PCIEPHY_REF clock

Hi Jonas, On 5/1/24 6:22 PM, Jonas Karlman wrote: rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the SCLK_PCIEPHY_REF clock. The existing enable/disable ops for SCLK_PCIEPHY_REF currently force use of 24 MHz parent and rate. Add improved support for setting parent and rat

Re: [PATCH v2 03/22] clk: rockchip: rk3399: Improve support for SCLK_PCIEPHY_REF clock

On 2024/5/2 00:22, Jonas Karlman wrote: rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the SCLK_PCIEPHY_REF clock. The existing enable/disable ops for SCLK_PCIEPHY_REF currently force use of 24 MHz parent and rate. Add improved support for setting parent and rate of the

[PATCH v2 03/22] clk: rockchip: rk3399: Improve support for SCLK_PCIEPHY_REF clock

rk3399-nanopi-4.dtsi try to set parent of and set rate to 100 MHz of the SCLK_PCIEPHY_REF clock. The existing enable/disable ops for SCLK_PCIEPHY_REF currently force use of 24 MHz parent and rate. Add improved support for setting parent and rate of the pciephy refclk to driver to better support a