j721e board includes 2 instances of TPS6594: - Primary PMIC - Secondary PMIC
Add AVS class0 in u-boot SPL. AVS is supported only on CPU rail: vdd_cpu_avs. This rail is supplied by the primary PMIC: tps659413 This rail is supplied by a dual-phased buck: buck12. Other PMICs rails are not AVS capable. Each PMIC includes a Watchdog that is active by default at boot. This would issue a platform reset unless pmic GPIO8 is driven or this is handled by SW. Watchdog driver is not required for identified use of this product. This software disable inside u-boot avoids parasitic wd reset. GPIO8 can then be used for other purpose. Board documentation: Link: https://www.ti.com/tool/J721EXSOMXEVM Signed-off-by: Jerome Neanne <jnea...@baylibre.com> --- .../k3-j721e-common-proc-board-u-boot.dtsi | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index 867ec2bb1a..a57d491689 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -79,6 +79,14 @@ chipid@43000014 { bootph-pre-ram; }; + + mcu_i2c0: i2c@40b00000 { + status = "okay"; + tps65941_wd: tps65941-wd@12 { + compatible = "ti,tps65941_watchdog"; + reg = <0x12>; + }; + }; }; &secure_proxy_main { @@ -170,6 +178,19 @@ &wkup_i2c0 { bootph-pre-ram; + tps659413: tps659413@48 { + bootph-pre-ram; + compatible = "ti,tps659413"; + + regulators { + bootph-pre-ram; + bucka12_reg: buck12 { + }; + }; + }; + tps659411: tps659411@4c { + compatible = "ti,tps659411"; + }; }; &main_i2c0 { -- 2.34.1
