Re: [PATCH v2 1/1] riscv: define a cache line size for the generic CPU

On Sat, Jul 22, 2023 at 12:01 AM Heinrich Schuchardt wrote: > > The USB 3.0 driver xhci-mem.c requires CONFIG_SYS_CACHELINE_SIZE to be set. > > Define the cache line size for QEMU on RISC-V to be 64 bytes. > > Signed-off-by: Heinrich Schuchardt > --- > v2: > Select SYS_CACHE_SHIFT_6 for G

[PATCH v2 1/1] riscv: define a cache line size for the generic CPU

The USB 3.0 driver xhci-mem.c requires CONFIG_SYS_CACHELINE_SIZE to be set. Define the cache line size for QEMU on RISC-V to be 64 bytes. Signed-off-by: Heinrich Schuchardt --- v2: Select SYS_CACHE_SHIFT_6 for GENERIC_RISCV and not for TARGET_QEMU_VIRT (as suggested by Bin) ---