On Sun, Nov 22, 2020 at 01:03:44PM +, Hugh Cole-Baker wrote:
> SPI flash on this machine is located on bus 1, default to using bus 1
> for SPI flash and stop aliasing it to bus 0.
>
> Signed-off-by: Hugh Cole-Baker
> Suggested-by: Simon Glass
> Fixes: c4cea2bb ("rockchip: Enable building a
SPI flash on this machine is located on bus 1, default to using bus 1
for SPI flash and stop aliasing it to bus 0.
Signed-off-by: Hugh Cole-Baker
Suggested-by: Simon Glass
Fixes: c4cea2bb ("rockchip: Enable building a SPI ROM image on bob")
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(no changes since v1)
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