Update the bindings doc for Exynos DW MMC block to follow the upstream
example and reflect the latest changes made in corresponding Linux
kernel bindings.
Signed-off-by: Sam Protsenko <semen.protse...@linaro.org>
---
doc/device-tree-bindings/exynos/dwmmc.txt | 46 +++++++++++++----------
1 file changed, 27 insertions(+), 19 deletions(-)
diff --git a/doc/device-tree-bindings/exynos/dwmmc.txt
b/doc/device-tree-bindings/exynos/dwmmc.txt
index 694d1959162c..d90792be8599 100644
--- a/doc/device-tree-bindings/exynos/dwmmc.txt
+++ b/doc/device-tree-bindings/exynos/dwmmc.txt
@@ -12,7 +12,9 @@ SOC specific and Board specific properties are channel
specific.
Required SoC Specific Properties:
- compatible: should be
- - samsung,exynos-dwmmc: for exynos platforms
+ - samsung,exynos4412-dw-mshc: for Exynos4 platforms
+ - samsung,exynos-dwmmc: for Exynos5 platforms
+ - samsung,exynos7-dw-mshc-smu: for Exynos7 platforms (with SMU block)
- reg: physical base address of the controller and length of memory mapped
region.
@@ -23,32 +25,38 @@ Required Board Specific Properties:
- #address-cells: should be 1.
- #size-cells: should be 0.
-- samsung,bus-width: The width of the bus used to interface the devices
+- bus-width: The width of the bus used to interface the devices
supported by DWC_mobile_storage (SD-MMC/EMMC/SDIO).
. Typically the bus width is 4 or 8.
-- samsung,timing: The timing values to be written into the
- Drv/sample clock selection register of corresponding channel.
- . It is comprised of 3 values corresponding to the 3 fileds
- 'SelClk_sample', 'SelClk_drv' and 'DIVRATIO' of CLKSEL register.
- . SelClk_sample: Select sample clock among 8 shifted clocks.
- . SelClk_drv: Select drv clock among 8 shifted clocks.
- . DIVRATIO: Clock Divide ratio select.
- . The above 3 values are used by the clock phase shifter.
+- samsung,dw-mshc-ciu-div: The divider value for the card interface unit (ciu)
+ clock (0..7).
+- samsung,dw-mshc-sdr-timing: The timing values for single data rate (SDR) mode
+ operation.
+ . First value is CIU clock phase shift value for TX mode (0..7).
+ . Second value is CIU clock phase shift value for RX mode (0..7).
+- samsung,dw-mshc-ddr-timing: The timing values for double data rate (DDR) mode
+ operation. If missing, values from samsung,dw-mshc-sdr-timing are used.
+ . First value is CIU clock phase shift value for TX mode (0..7).
+ . Second value is CIU clock phase shift value for RX mode (0..7).
Example:
mmc@12200000 {
- samsung,bus-width = <8>;
- samsung,timing = <1 3 3>;
- samsung,removable = <1>;
-}
+ bus-width = <8>;
+ non-removable;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <1 3>;
+ samsung,dw-mshc-ddr-timing = <0 2>;
+};
+
In the above example,
. The bus width is 8
- . Timing is comprised of 3 values as explained below
+ . Divider value for CLKSEL register is 3. The CIU clock rate will be
+ calculated as SDCLKIN / (3 + 1).
+ . SDR and DDR timings are comprised of 2 values as explained below
1 - SelClk_sample
3 - SelClk_drv
- 3 - DIVRATIO
- . The 'removable' flag indicates whether the the particilar device
+ . The 'non-removable' flag indicates whether the particular device
cannot be removed (always present) or it is a removable device.
- 1 - Indicates that the device is removable.
- 0 - Indicates that the device cannot be removed.
+ Flag is present - Indicates that the device cannot be removed.
+ Flag is not present - Indicates that the device is removable.
--
2.39.2
