On 3/10/22 3:50 PM, Sean Anderson wrote:
> This register holds "pstate" which includes (among other things) the
> instruction mode the CPU was in when the exception was taken. This is
> necessary to correctly interpret instructions at elr.
>
> Signed-off-by: Sean Anderson
> ---
>
> Changes
This register holds "pstate" which includes (among other things) the
instruction mode the CPU was in when the exception was taken. This is
necessary to correctly interpret instructions at elr.
Signed-off-by: Sean Anderson
---
Changes in v2:
- New
arch/arm/cpu/armv8/exceptions.S | 5
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