Re: [PATCH v3 2/2] arm: stm32mp: activate data cache on DDR in SPL

Hi One typo below On 4/24/20 8:24 PM, Patrick Delaunay wrote: > Activate cache on DDR to improves the accesses to DDR used by SPL: s/improves/improve > - CONFIG_SPL_BSS_START_ADDR > - CONFIG_SYS_SPL_MALLOC_START > > Cache is configured only when DDR is fully initialized, > to avoid speculative ac

[PATCH v3 2/2] arm: stm32mp: activate data cache on DDR in SPL

Activate cache on DDR to improves the accesses to DDR used by SPL: - CONFIG_SPL_BSS_START_ADDR - CONFIG_SYS_SPL_MALLOC_START Cache is configured only when DDR is fully initialized, to avoid speculative access and issue in get_ram_size(). Data cache is deactivated at the end of SPL, to flush the da