This is not obvious so add a little note about how it works.
Signed-off-by: Simon Glass <s...@chromium.org>
Reviewed-by: Bin Meng <bmeng...@gmail.com>
---
(no changes since v1)
doc/board/coreboot/coreboot.rst | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst
index 4a5f101cad2..0fe95af56d2 100644
--- a/doc/board/coreboot/coreboot.rst
+++ b/doc/board/coreboot/coreboot.rst
@@ -71,3 +71,32 @@ Memory map
(typically redirects to 7ab10030 or similar)
500 Location of coreboot sysinfo table, used during startup
==========
==================================================================
+
+
+Debug UART
+----------
+
+It is possible to enable the debug UART with coreboot. To do this, use the
+info from the cbsysinfo command to locate the UART base. For example::
+
+ => cbsysinfo
+ ...
+ Serial I/O port: 00000000
+ base : 00000000
+ pointer : 767b51bc
+ type : 2
+ base : fe03e000
+ baud : 0d115200
+ regwidth : 4
+ input_hz : 0d1843200
+ PCI addr : 00000010
+ ...
+
+Here you can see that the UART base is fe03e000, regwidth is 4 (1 << 2) and the
+input clock is 1843200. So you can add the following CONFIG options::
+
+ CONFIG_DEBUG_UART=y
+ CONFIG_DEBUG_UART_BASE=fe03e000
+ CONFIG_DEBUG_UART_CLOCK=1843200
+ CONFIG_DEBUG_UART_SHIFT=2
+ CONFIG_DEBUG_UART_ANNOUNCE=y
--
2.40.1.521.gf1e218fcd8-goog
