On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote:
> If DISP1 is a PLLD/D2 child, it cannot go over 370MHz. The cause
> of this is not quite clear. This can be overcomed by further
> halving the PLLD/D2 if the target parent rate is over 800MHz.
> This way DISP1 and DSI clocks will have the
If DISP1 is a PLLD/D2 child, it cannot go over 370MHz. The cause
of this is not quite clear. This can be overcomed by further
halving the PLLD/D2 if the target parent rate is over 800MHz.
This way DISP1 and DSI clocks will have the same frequency. The
shift divider in this case has to be calculated
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