From: Nikita Shubin <n.shu...@yadro.com> On Xilinx AXI Ethernet we can have both "internal" (PCS) and "external" phy's.
As per Xilinx SPEC's they should have different addresses on MDIO bus. In Linux we have a phylink mechanism to handle this particular situation. PCS has to be at least BMCR_ANENABLE after Core bringup. Without this patch we can't bringup the Xilinx AXI Ethernet in u-boot properly. Nikita Shubin (1): net: xilinx: handle internal PHY/PCS drivers/net/xilinx_axi_emac.c | 50 +++++++++++++++++++++++++++++++++-- 1 file changed, 48 insertions(+), 2 deletions(-) -- 2.35.1
