On 5/31/23 00:08, Emanuele Ghidoli wrote:
From: Emanuele Ghidoli
On Cortex-R5 flushing and disabling cache is not enough to avoid
cache and memory incoherence.
In particular, when the cache is enabled after a disable, and if there
are entry in the cache the value from the cache is used instead
From: Emanuele Ghidoli
On Cortex-R5 flushing and disabling cache is not enough to avoid
cache and memory incoherence.
In particular, when the cache is enabled after a disable, and if there
are entry in the cache the value from the cache is used instead of the
value from the memory. This, in part
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