On 4/5/22 11:09, Francesco Dolcini wrote:
On Mon, Apr 04, 2022 at 09:56:50PM +0200, Marek Vasut wrote:
On 4/4/22 16:53, Francesco Dolcini wrote:
On Mon, Apr 04, 2022 at 03:39:35PM +0200, Marek Vasut wrote:
--- a/arch/arm/mach-imx/mx6/ddr.c
+++ b/arch/arm/mach-imx/mx6/ddr.c
@@ -1526,6 +1526,8 @
On Mon, Apr 04, 2022 at 09:56:50PM +0200, Marek Vasut wrote:
> On 4/4/22 16:53, Francesco Dolcini wrote:
> > On Mon, Apr 04, 2022 at 03:39:35PM +0200, Marek Vasut wrote:
> > > > --- a/arch/arm/mach-imx/mx6/ddr.c
> > > > +++ b/arch/arm/mach-imx/mx6/ddr.c
> > > > @@ -1526,6 +1526,8 @@ void mx6_ddr3_c
On 4/4/22 16:53, Francesco Dolcini wrote:
Hello Marek,
thanks for your review.
On Mon, Apr 04, 2022 at 03:39:35PM +0200, Marek Vasut wrote:
On 4/4/22 10:51, Francesco Dolcini wrote:
Wait 1ms before issuing the first MRS command to write DDR3 Mode
registers.
There is a requirement to wait mini
Hello Marek,
thanks for your review.
On Mon, Apr 04, 2022 at 03:39:35PM +0200, Marek Vasut wrote:
> On 4/4/22 10:51, Francesco Dolcini wrote:
> > Wait 1ms before issuing the first MRS command to write DDR3 Mode
> > registers.
> >
> > There is a requirement to wait minimum of Reset CKE Exit time,
On 4/4/22 10:51, Francesco Dolcini wrote:
Wait 1ms before issuing the first MRS command to write DDR3 Mode
registers.
There is a requirement to wait minimum of Reset CKE Exit time, tXPR,
with tXPR = max(tXS, 5tCK) and to wait 500 useconds after reset is
de-asserted. It seems that for some reason
Wait 1ms before issuing the first MRS command to write DDR3 Mode
registers.
There is a requirement to wait minimum of Reset CKE Exit time, tXPR,
with tXPR = max(tXS, 5tCK) and to wait 500 useconds after reset is
de-asserted. It seems that for some reason this is not enforced by the
MMDC controller
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