Re: [SPAM] rk3399 TPL memory setup code triggers clock frequency limit assertion

2022-08-08 Thread Xavier Drudis Ferran
El Mon, Aug 08, 2022 at 11:22:49PM +0530, Jagan Teki deia: > > If I remember correctly when I work with YouMin on LPDDR4 the initial > code to start to check with was 50MHz (It was not working at that time > with 48MHz). Not sure what to make other changes to fix that to try on > 48MHz. > Not su

Re: [SPAM] rk3399 TPL memory setup code triggers clock frequency limit assertion

2022-08-08 Thread Jagan Teki
On Mon, Aug 8, 2022 at 9:46 PM Michal Suchánek wrote: > > On Mon, Aug 08, 2022 at 04:28:33PM +0200, Xavier Drudis Ferran wrote: > > El Sun, Aug 07, 2022 at 04:44:04PM +0200, Michal Suchánek deia: > > > Hello, > > > > > > when compiled with clock debug rk3399 cannot be booted because memory > > > s

Re: [SPAM] rk3399 TPL memory setup code triggers clock frequency limit assertion

2022-08-08 Thread Michal Suchánek
On Mon, Aug 08, 2022 at 04:28:33PM +0200, Xavier Drudis Ferran wrote: > El Sun, Aug 07, 2022 at 04:44:04PM +0200, Michal Suchánek deia: > > Hello, > > > > when compiled with clock debug rk3399 cannot be booted because memory > > setup code triggers clock assertion: > > > > U-Boot TPL 2022.07-0003

Re: [SPAM] rk3399 TPL memory setup code triggers clock frequency limit assertion

2022-08-08 Thread Xavier Drudis Ferran
El Sun, Aug 07, 2022 at 04:44:04PM +0200, Michal Suchánek deia: > Hello, > > when compiled with clock debug rk3399 cannot be booted because memory > setup code triggers clock assertion: > > U-Boot TPL 2022.07-00038-g61e11a8e9f-dirty (Aug 07 2022 - 16:13:17) > TPL PLL at ff76: fbdiv=50, refdiv