[U-Boot] [PATCH] ARM: DRA7: Change configuration to prevent DDR reset control from EMIF

DRA7/AM57xx devices can be operated in many different configurations. When the SoC is supposed to support a configuration where low power mode state may involve the SoC completely powered off and DDR is in self refresh, SoC EMIF controller should not be the master of the reset signal and an

Re: [U-Boot] [PATCH] ARM: DRA7: Change configuration to prevent DDR reset control from EMIF

On Tue, Jun 16, 2015 at 08:29:01AM -0500, Nishanth Menon wrote: DRA7/AM57xx devices can be operated in many different configurations. When the SoC is supposed to support a configuration where low power mode state may involve the SoC completely powered off and DDR is in self refresh, SoC EMIF