On RCar M3 and on RCar H3 newer than and not including ES1.0, the SD clock
must be divided by 4 rather than 2 because a hardware workaround present
only in the H3 ES1.0 has been removed from these chips. U-Boot currently
only supports M3 and H3 ES 2.0 and newer, so configure the SD pre-divider
to 4 to prevent SD instability.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: Nobuhiro Iwamatsu <iwama...@nigauri.org>
---
board/renesas/salvator-x/salvator-x.c | 8 ++++----
board/renesas/ulcb/ulcb.c | 8 ++++----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/board/renesas/salvator-x/salvator-x.c
b/board/renesas/salvator-x/salvator-x.c
index 2695de5dbf..e260117802 100644
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -74,10 +74,10 @@ int board_early_init_f(void)
/* SDHI0, 3 */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314 | SD3_MSTP311);
- writel(0, SD0CKCR);
- writel(0, SD1CKCR);
- writel(0, SD2CKCR);
- writel(0, SD3CKCR);
+ writel(1, SD0CKCR);
+ writel(1, SD1CKCR);
+ writel(1, SD2CKCR);
+ writel(1, SD3CKCR);
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c
index 2b6cc612c8..dc23228f4f 100644
--- a/board/renesas/ulcb/ulcb.c
+++ b/board/renesas/ulcb/ulcb.c
@@ -72,10 +72,10 @@ int board_early_init_f(void)
/* SDHI0 */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314);
- writel(0, SD0CKCR);
- writel(0, SD1CKCR);
- writel(0, SD2CKCR);
- writel(0, SD3CKCR);
+ writel(1, SD0CKCR);
+ writel(1, SD1CKCR);
+ writel(1, SD2CKCR);
+ writel(1, SD3CKCR);
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
--
2.13.2
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