On 01/22/2014 01:21 PM, Stephen Warren wrote:
> From: Jimmy Zhang
>
> Based on the Tegra114 TRM, the system clock (which is the AVP clock) can
> run up to 275MHz. On power on, the default sytem clock source is set to
> PLLP_OUT0. In function clock_early_init(), PLLP_OUT0 will be set to
> 408MHz w
From: Jimmy Zhang
Based on the Tegra114 TRM, the system clock (which is the AVP clock) can
run up to 275MHz. On power on, the default sytem clock source is set to
PLLP_OUT0. In function clock_early_init(), PLLP_OUT0 will be set to
408MHz which is beyond system clock's upper limit.
The fix is to
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