Re: [U-Boot] [PATCH] EXYNOS: SPI: Minimise access to SPI FIFO level

On Fri, Mar 22, 2013 at 8:09 AM, Rajeshwari Shinde rajeshwar...@samsung.com wrote: Accessing SPI registers is slow, but access to the FIFO level register in particular seems to be extraordinarily expensive (I measure up to 600ns). Perhaps it is required to synchronise with the SPI byte output

[U-Boot] [PATCH] EXYNOS: SPI: Minimise access to SPI FIFO level

Accessing SPI registers is slow, but access to the FIFO level register in particular seems to be extraordinarily expensive (I measure up to 600ns). Perhaps it is required to synchronise with the SPI byte output logic which might run at 1/8th of the 40MHz SPI speed (just a guess). Reduce access to