T1040 RM specifies CLK_ADJUST as 5 bits starting at bit pos 9
in DDR_DDR_SDRAM_CLK_CNTL, update code to match.
Signed-off-by: Joakim Tjernlund
---
drivers/ddr/fsl/ctrl_regs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 09/02/2015 06:41 AM, Joakim Tjernlund wrote:
> T1040 RM specifies CLK_ADJUST as 5 bits starting at bit pos 9
> in DDR_DDR_SDRAM_CLK_CNTL, update code to match.
>
> Signed-off-by: Joakim Tjernlund
> ---
> drivers/ddr/fsl/ctrl_regs.c | 2 +-
> 1 file changed, 1
On 09/02/2015 09:42 AM, Joakim Tjernlund wrote:
> On Wed, 2015-09-02 at 09:34 -0500, York Sun wrote:
>>
>> On 09/02/2015 09:31 AM, Joakim Tjernlund wrote:
>>> On Wed, 2015-09-02 at 08:35 -0500, York Sun wrote:
On 09/02/2015 06:41 AM, Joakim Tjernlund wrote:
> T1040 RM specifies
On Wed, 2015-09-02 at 09:51 -0500, York Sun wrote:
>
> On 09/02/2015 09:42 AM, Joakim Tjernlund wrote:
> > On Wed, 2015-09-02 at 09:34 -0500, York Sun wrote:
> > >
> > > On 09/02/2015 09:31 AM, Joakim Tjernlund wrote:
> > > > On Wed, 2015-09-02 at 08:35 -0500, York Sun wrote:
> > > > >
> > > >
On Wed, 2015-09-02 at 08:35 -0500, York Sun wrote:
>
> On 09/02/2015 06:41 AM, Joakim Tjernlund wrote:
> > T1040 RM specifies CLK_ADJUST as 5 bits starting at bit pos 9
> > in DDR_DDR_SDRAM_CLK_CNTL, update code to match.
> >
> > Signed-off-by: Joakim Tjernlund
>
On 09/02/2015 09:31 AM, Joakim Tjernlund wrote:
> On Wed, 2015-09-02 at 08:35 -0500, York Sun wrote:
>>
>> On 09/02/2015 06:41 AM, Joakim Tjernlund wrote:
>>> T1040 RM specifies CLK_ADJUST as 5 bits starting at bit pos 9
>>> in DDR_DDR_SDRAM_CLK_CNTL, update code to match.
>>>
>>> Signed-off-by:
On Wed, 2015-09-02 at 09:34 -0500, York Sun wrote:
>
> On 09/02/2015 09:31 AM, Joakim Tjernlund wrote:
> > On Wed, 2015-09-02 at 08:35 -0500, York Sun wrote:
> > >
> > > On 09/02/2015 06:41 AM, Joakim Tjernlund wrote:
> > > > T1040 RM specifies CLK_ADJUST as 5 bits starting at bit pos 9
> > > >
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