From: Alexey Brodkin
Current implementation works fine for bus width = 16 bits because we
never get into "if" branch.
If one sets width to 8 bits there will be 2 consequent data accesses
(read/write):
1. Correct data access for 8-bit bus
2. Unconditional (and in this case incorrect) data access
2013/1/2 Alexey Brodkin :
> From: Alexey Brodkin
>
> Current implementation works fine for bus width = 16 bits because we
> never get into "if" branch.
>
> If one sets width to 8 bits there will be 2 consequent data accesses
> (read/write):
> 1. Correct data access for 8-bit bus
> 2. Unconditional
Hi,
2013/1/2 Алексей Бродкин :
> The reason for latter modification is to make code more readable.
> Do you think if I may submit this as a cosmetic change separately?
If you mean create 3rd patch then no.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Mainta
The reason for latter modification is to make code more readable.
Do you think if I may submit this as a cosmetic change separately?
2013/1/2 Michal Simek
> 2013/1/2 Alexey Brodkin :
> > From: Alexey Brodkin
> >
> > Current implementation works fine for bus width = 16 bits because we
> > never
Actually I meant to respin both patches.
1. Only add "else" thread for "ace_writew", keeping "ace_readw" unchanged
2. Replace "in16"/"out16" with "readw"/"writew"
2013/1/2 Michal Simek
> Hi,
>
> 2013/1/2 Алексей Бродкин :
> > The reason for latter modification is to make code more readable.
> >
Dear Alexey Brodkin,
In message <1357137512-8618-1-git-send-email-alexey.brod...@gmail.com> you
wrote:
> From: Alexey Brodkin
>
> Current implementation works fine for bus width = 16 bits because we
> never get into "if" branch.
>
> If one sets width to 8 bits there will be 2 consequent data a
Hi Wolfgang,
2013/1/2 Wolfgang Denk :
> Dear Alexey Brodkin,
>
> In message <1357137512-8618-1-git-send-email-alexey.brod...@gmail.com> you
> wrote:
>> From: Alexey Brodkin
>>
>> Current implementation works fine for bus width = 16 bits because we
>> never get into "if" branch.
>>
>> If one sets
Dear Michal Simek,
In message
you wrote:
>
> > You say, if one sets width to 8 bits, then the code fails when the bus
> > is actually 16 bits wide?
...
> Here is that function with my comment about missing "else".
> In ace_writew function we shouldn't write 16bit value when width is 8.
> (It pr
2013/1/3 Wolfgang Denk :
> Dear Michal Simek,
>
> In message
> you
> wrote:
>>
>> > You say, if one sets width to 8 bits, then the code fails when the bus
>> > is actually 16 bits wide?
> ...
>> Here is that function with my comment about missing "else".
>> In ace_writew function we shouldn't wr
Dear Michal Simek,
In message
you wrote:
>
> > I see. Well, I think the commit message is not really clear. I
> > definitely misunderstood it. Maybe it can be improved?
>
> Yep.
Thanks.
> btw: is there any coding style rule about this second function
>
> Current (simplified) case.
> stati
2013/1/3 Wolfgang Denk :
> Dear Michal Simek,
>
> In message
> you
> wrote:
>>
>> > I see. Well, I think the commit message is not really clear. I
>> > definitely misunderstood it. Maybe it can be improved?
>>
>> Yep.
>
> Thanks.
>
>> btw: is there any coding style rule about this second func
Dear Alexey Brodkin,
In message <1357137512-8618-1-git-send-email-alexey.brod...@gmail.com> you
wrote:
> From: Alexey Brodkin
>
> Current implementation works fine for bus width = 16 bits because we
> never get into "if" branch.
>
> If one sets width to 8 bits there will be 2 consequent data a
Hi Wolfgang,
I've already sent V2 patch with only 1 chunk and updated comments to the
mailing list.
-Alexey
03.01.2013 16:00 пользователь "Wolfgang Denk" написал:
> Dear Alexey Brodkin,
>
> In message <1357137512-8618-1-git-send-email-alexey.brod...@gmail.com>
> you wrote:
> > From: Alexey Brod
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