On Mar 30, 2010, at 10:46 AM, Timur Tabi wrote:
> On Mon, Mar 29, 2010 at 11:21 PM, Kumar Gala
> wrote:
>>> Why do we need BATL_MEMCOHERENCE on 8641 but not on 8610?
>>
>> dual core on 8641, single core on 8610.
>
> The 8610 does lots of DMA for audio and video. Don't we need
> coherence for
On Mon, Mar 29, 2010 at 11:21 PM, Kumar Gala wrote:
>> Why do we need BATL_MEMCOHERENCE on 8641 but not on 8610?
>
> dual core on 8641, single core on 8610.
The 8610 does lots of DMA for audio and video. Don't we need
coherence for that? I read the e600 manual, but I couldn't glean
whether we n
On Mar 29, 2010, at 10:40 PM, Timur Tabi wrote:
> On Mon, Mar 29, 2010 at 10:02 PM, Kumar Gala
> wrote:
>
>> + * We also assume that the XBL bits are ignored by the processor (even if
>> set)
>> + * if extended BAT addressing is disabled.
>
> Since we don't read/modify/write that BATs, this
On Mon, Mar 29, 2010 at 10:02 PM, Kumar Gala wrote:
> + * We also assume that the XBL bits are ignored by the processor (even if
> set)
> + * if extended BAT addressing is disabled.
Since we don't read/modify/write that BATs, this comment is probably
not true any more.
> -#define BATU_SIZE(x)
From: Timur Tabi
After determining how much DDR is actually in the system, set DBAT0 and
IBAT0 accordingly. This ensures that the CPU won't attempt to access
(via speculation) addresses outside of actual memory.
On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized to 2GB and
kept
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