Up until now this driver only worked with data cache disabled.
To make it work with enabled data cache following changes were required:
* Implement all accesses to shared structures between CPU and GMAC via
uncached reads/writes (readl/writel).
* Flush cache for data passed from CPU to GMAC
*
Hi Alexey,
* Implement all accesses to shared structures between CPU and GMAC via
uncached reads/writes (readl/writel).
I don't know how ARC exactly implements this for u-boot, but AFAIK,
readl/writel are meant for 'strongly ordered' I/O writes, not necessarily
uncached. The uncached part
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