On Apr 23, 2011, at 1:45 PM, Wolfgang Denk wrote:
Dear Kumar Gala,
In message 54ce1181-5449-4fbf-9402-df5d4e99e...@kernel.crashing.org you
wrote:
On Apr 22, 2011, at 6:50 AM, Tabi Timur-B04825 wrote:
On Thu, Apr 21, 2011 at 1:59 PM, Kumar Gala ga...@kernel.crashing.org
wrote:
Dear Kumar Gala,
In message 54ce1181-5449-4fbf-9402-df5d4e99e...@kernel.crashing.org you wrote:
On Apr 22, 2011, at 6:50 AM, Tabi Timur-B04825 wrote:
On Thu, Apr 21, 2011 at 1:59 PM, Kumar Gala ga...@kernel.crashing.org
wrote:
Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms
On Thu, Apr 21, 2011 at 1:59 PM, Kumar Gala ga...@kernel.crashing.org wrote:
Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because
different SoCs have different divisor amounts. All the PQ3 parts are
/8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32.
Shouldn't there also be
On Fri, 22 Apr 2011 08:26:55 -0500
Kumar Gala ga...@kernel.crashing.org wrote:
On Apr 22, 2011, at 6:50 AM, Tabi Timur-B04825 wrote:
On Thu, Apr 21, 2011 at 1:59 PM, Kumar Gala ga...@kernel.crashing.org
wrote:
Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because
On Fri, Apr 22, 2011 at 8:26 AM, Kumar Gala ga...@kernel.crashing.org wrote:
Shouldn't there also be a README update to document this option?
I think its self evident what it is.
I have to disagree. Without reading the patch description, it's hard
to know what value to choose for this macro.
Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because
different SoCs have different divisor amounts. All the PQ3 parts are
/8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/cpu/mpc85xx/cpu.c|
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