On 05/12/2014 10:50 PM, Prabhakar Kushwaha wrote:
> The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/P2010
> where max DDR data width supported is 64bit.
>
> Add dynamic DDR size adjustment in second stage boot loader execution.
>
> Signed-off-by: Prabhakar Kushwaha
> ---
>
The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/P2010
where max DDR data width supported is 64bit.
Add dynamic DDR size adjustment in second stage boot loader execution.
Signed-off-by: Prabhakar Kushwaha
---
arch/powerpc/cpu/mpc85xx/cpu.c |7 ++-
1 file changed, 6 i
2 matches
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