On Jul 15, 2010, at 11:52 AM, Kumar Gala wrote:
> The CoreNet style platforms can have a L3 cache that fronts the memory
> controllers. Enable that cache as well as add information into the
> device tree about it.
>
> Signed-off-by: Kumar Gala
> Signed-off-by: Dave Liu
> Signed-off-by: Becky
The CoreNet style platforms can have a L3 cache that fronts the memory
controllers. Enable that cache as well as add information into the
device tree about it.
Signed-off-by: Kumar Gala
Signed-off-by: Dave Liu
Signed-off-by: Becky Bruce
Signed-off-by: Roy Zang
Signed-off-by: Timur Tabi
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