Hi Philipp,
On 08/31/2017 06:25 PM, Andy Yan wrote:
Hi Philipp:
On 2017年08月28日 04:21, Dr. Philipp Tomsich wrote:
On 23 Aug 2017, at 09:26, Andy Yan wrote:
commit 4bebf94e8544("rockchip: clk: rk3368: do not change
CPLL/GPLL before returning to BROM") limits the pll
Hi Philipp:
On 2017年08月28日 04:21, Dr. Philipp Tomsich wrote:
On 23 Aug 2017, at 09:26, Andy Yan wrote:
commit 4bebf94e8544("rockchip: clk: rk3368: do not change
CPLL/GPLL before returning to BROM") limits the pll can only
be setup in SPL stage, but there are still
> On 23 Aug 2017, at 09:26, Andy Yan wrote:
>
> commit 4bebf94e8544("rockchip: clk: rk3368: do not change
> CPLL/GPLL before returning to BROM") limits the pll can only
> be setup in SPL stage, but there are still some rk3368 based
> boards have not use SPL yet, so they
Hi Andy
On 23 August 2017 at 01:26, Andy Yan wrote:
> commit 4bebf94e8544("rockchip: clk: rk3368: do not change
> CPLL/GPLL before returning to BROM") limits the pll can only
> be setup in SPL stage, but there are still some rk3368 based
> boards have not use SPL yet, so
commit 4bebf94e8544("rockchip: clk: rk3368: do not change
CPLL/GPLL before returning to BROM") limits the pll can only
be setup in SPL stage, but there are still some rk3368 based
boards have not use SPL yet, so they need run rkclk_init to
setup the pll in full u-boot stage, otherwise the
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