Re: [U-Boot] [PATCH] sunxi: set up PLL1 on sun6i+ without use dividers

2017-04-11 Thread Maxime Ripard
On Mon, Apr 10, 2017 at 04:43:00PM +0800, icen...@aosc.io wrote: > 在 2017-04-10 14:59，Maxime Ripard 写道： > > On Mon, Apr 10, 2017 at 12:19:41AM +0800, Icenowy Zheng wrote: > > > According to the researching result of Ondrej Jirman, the factor M of > > > PLL1 shouldn't be used and the factor P should

Re: [U-Boot] [PATCH] sunxi: set up PLL1 on sun6i+ without use dividers

2017-04-10 Thread icenowy
在 2017-04-10 14:59，Maxime Ripard 写道： On Mon, Apr 10, 2017 at 12:19:41AM +0800, Icenowy Zheng wrote: According to the researching result of Ondrej Jirman, the factor M of PLL1 shouldn't be used and the factor P should be used only if the intended frequency is lower than 288MHz. This is proven by

Re: [U-Boot] [PATCH] sunxi: set up PLL1 on sun6i+ without use dividers

2017-04-10 Thread Maxime Ripard
On Mon, Apr 10, 2017 at 12:19:41AM +0800, Icenowy Zheng wrote: > According to the researching result of Ondrej Jirman, the factor M of > PLL1 shouldn't be used and the factor P should be used only if the > intended frequency is lower than 288MHz. This is proven by the > clk-sun8iw7_tbl.c in the BSP

[U-Boot] [PATCH] sunxi: set up PLL1 on sun6i+ without use dividers

2017-04-09 Thread Icenowy Zheng
According to the researching result of Ondrej Jirman, the factor M of PLL1 shouldn't be used and the factor P should be used only if the intended frequency is lower than 288MHz. This is proven by the clk-sun8iw7_tbl.c in the BSP source code -- in there the M value is always 0 and the maximum freque