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On 04/05/2017 10:18 AM, Felipe Balbi wrote:
>
> Hi,
>
> Marek Vasut writes:
> Merely using dma_alloc_coherent does not ensure that there is no stale
> data left in the caches for the allocated DMA buffer (i.e. that the
> affected cacheline may still be dirty).
>
On 04/05/2017 12:57 PM, Dr. Philipp Tomsich wrote:
>
>> On 05 Apr 2017, at 12:25, Marek Vasut wrote:
>>
>> On 04/04/2017 10:26 PM, Dr. Philipp Tomsich wrote:
>>>
On 04 Apr 2017, at 22:09, Marek Vasut wrote:
> The DWC3 flush expands to a
On 04/05/2017 10:15 AM, Felipe Balbi wrote:
>
> Hi,
>
> Marek Vasut writes:
>>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
>>> index b2c7eb1..f58c7ba 100644
>>> --- a/drivers/usb/dwc3/core.c
>>> +++ b/drivers/usb/dwc3/core.c
>>> @@ -125,6 +125,8 @@ static
> On 05 Apr 2017, at 12:25, Marek Vasut wrote:
>
> On 04/04/2017 10:26 PM, Dr. Philipp Tomsich wrote:
>>
>>> On 04 Apr 2017, at 22:09, Marek Vasut wrote:
>>>
The DWC3 flush expands to a clean+invalidate. It is not wrong, as long as
it is used as in my
On 04/04/2017 10:26 PM, Dr. Philipp Tomsich wrote:
>
>> On 04 Apr 2017, at 22:09, Marek Vasut wrote:
>>
>>> The DWC3 flush expands to a clean+invalidate. It is not wrong, as long as
>>> it is used as in my patch:
>>> a. before the first time data is expected to be written by the
Hi,
"Dr. Philipp Tomsich" writes:
Good point on the “long”, especially as I just copied this from other
occurences and it’s consistently wrong throughout DWC3 in U-Boot:
>>>
>>> Hrm, I thought the driver was ported over from Linux, so is this
Felipe,
> On 05 Apr 2017, at 10:18, Felipe Balbi wrote:
>
>>> Good point on the “long”, especially as I just copied this from other
>>> occurences and it’s consistently wrong throughout DWC3 in U-Boot:
>>
>> Hrm, I thought the driver was ported over from Linux,
Hi,
Marek Vasut writes:
Merely using dma_alloc_coherent does not ensure that there is no stale
data left in the caches for the allocated DMA buffer (i.e. that the
affected cacheline may still be dirty).
The original code was doing the following (on
Hi,
Marek Vasut writes:
>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
>> index b2c7eb1..f58c7ba 100644
>> --- a/drivers/usb/dwc3/core.c
>> +++ b/drivers/usb/dwc3/core.c
>> @@ -125,6 +125,8 @@ static struct dwc3_event_buffer
>>
> On 04 Apr 2017, at 22:09, Marek Vasut wrote:
>
>> The DWC3 flush expands to a clean+invalidate. It is not wrong, as long as
>> it is used as in my patch:
>> a. before the first time data is expected to be written by the peripheral
>> (i.e.
>> before the peripheral is
On 04/04/2017 09:56 PM, Dr. Philipp Tomsich wrote:
>
>> On 04 Apr 2017, at 21:01, Marek Vasut wrote:
>>
>>> Good point on the “long”, especially as I just copied this from other
>>> occurrences and it’s consistently wrong throughout DWC3 in U-Boot:
>>
>> Hrm, I thought the driver
> On 04 Apr 2017, at 21:01, Marek Vasut wrote:
>
>> Good point on the “long”, especially as I just copied this from other
>> occurrences and it’s consistently wrong throughout DWC3 in U-Boot:
>
> Hrm, I thought the driver was ported over from Linux, so is this broken
> in Linux
On 04/04/2017 07:46 PM, Dr. Philipp Tomsich wrote:
>
>> On 04 Apr 2017, at 18:15, Marek Vasut wrote:
>>
>> On 04/03/2017 07:49 PM, Philipp Tomsich wrote:
>>> Merely using dma_alloc_coherent does not ensure that there is no stale
>>> data left in the caches for the allocated DMA
> On 04 Apr 2017, at 18:15, Marek Vasut wrote:
>
> On 04/03/2017 07:49 PM, Philipp Tomsich wrote:
>> Merely using dma_alloc_coherent does not ensure that there is no stale
>> data left in the caches for the allocated DMA buffer (i.e. that the
>> affected cacheline may still be
On 04/03/2017 07:49 PM, Philipp Tomsich wrote:
> Merely using dma_alloc_coherent does not ensure that there is no stale
> data left in the caches for the allocated DMA buffer (i.e. that the
> affected cacheline may still be dirty).
>
> The original code was doing the following (on AArch64, which
Merely using dma_alloc_coherent does not ensure that there is no stale
data left in the caches for the allocated DMA buffer (i.e. that the
affected cacheline may still be dirty).
The original code was doing the following (on AArch64, which
translates a 'flush' into a 'clean + invalidate'):
#
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