The rk3228 and rk3328 Socs both have rmii interface, that might be used,
so add them for usage.
Signed-off-by: David Wu <david...@rock-chips.com>
---
drivers/net/gmac_rockchip.c | 115 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 115 insertions(+)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 4396ca1..5afc415 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -73,6 +73,41 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice
*dev)
return designware_eth_ofdata_to_platdata(dev);
}
+static int rk3228_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata,
+ struct dw_eth_dev *priv)
+{
+ struct rk322x_grf *grf;
+ int clk;
+ enum {
+ RK3228_GMAC_RMII_CLK_MASK = BIT(7),
+ RK3228_GMAC_RMII_CLK_2_5M = 0,
+ RK3228_GMAC_RMII_CLK_25M = BIT(7),
+
+ RK3228_GMAC_RMII_SPEED_MASK = BIT(2),
+ RK3228_GMAC_RMII_SPEED_10 = 0,
+ RK3228_GMAC_RMII_SPEED_100 = BIT(2),
+ };
+
+ switch (priv->phydev->speed) {
+ case 10:
+ clk = RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_RMII_SPEED_10;
+ break;
+ case 100:
+ clk = RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_RMII_SPEED_100;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
+ return -EINVAL;
+ }
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->mac_con[1],
+ RK3228_GMAC_RMII_CLK_MASK | RK3228_GMAC_RMII_SPEED_MASK,
+ clk);
+
+ return 0;
+}
+
static int rk3228_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
struct dw_eth_dev *priv)
{
@@ -134,6 +169,41 @@ static int rk3288_gmac_fix_rgmii_speed(struct
gmac_rockchip_platdata *pdata,
return 0;
}
+static int rk3328_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata,
+ struct dw_eth_dev *priv)
+{
+ struct rk3328_grf_regs *grf;
+ int clk;
+ enum {
+ RK3328_GMAC_RMII_CLK_MASK = BIT(7),
+ RK3328_GMAC_RMII_CLK_2_5M = 0,
+ RK3328_GMAC_RMII_CLK_25M = BIT(7),
+
+ RK3328_GMAC_RMII_SPEED_MASK = BIT(2),
+ RK3328_GMAC_RMII_SPEED_10 = 0,
+ RK3328_GMAC_RMII_SPEED_100 = BIT(2),
+ };
+
+ switch (priv->phydev->speed) {
+ case 10:
+ clk = RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_RMII_SPEED_10;
+ break;
+ case 100:
+ clk = RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_RMII_SPEED_100;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
+ return -EINVAL;
+ }
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] :
&grf->mac_con[1],
+ RK3328_GMAC_RMII_CLK_MASK | RK3328_GMAC_RMII_SPEED_MASK,
+ clk);
+
+ return 0;
+}
+
static int rk3328_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
struct dw_eth_dev *priv)
{
@@ -264,6 +334,28 @@ static int rv1108_gmac_fix_rmii_speed(struct
gmac_rockchip_platdata *pdata,
return 0;
}
+static void rk3228_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk322x_grf *grf;
+ enum {
+ RK3228_GRF_CON_RMII_MODE_MASK = BIT(11),
+ RK3228_GRF_CON_RMII_MODE_SEL = BIT(11),
+ RK3228_RMII_MODE_MASK = BIT(10),
+ RK3228_RMII_MODE_SEL = BIT(10),
+ RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
+ RK3228_GMAC_PHY_INTF_SEL_RMII = BIT(6),
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->mac_con[1],
+ RK3228_GRF_CON_RMII_MODE_MASK |
+ RK3228_RMII_MODE_MASK |
+ RK3228_GMAC_PHY_INTF_SEL_MASK,
+ RK3228_GRF_CON_RMII_MODE_SEL |
+ RK3228_RMII_MODE_SEL |
+ RK3228_GMAC_PHY_INTF_SEL_RMII);
+}
+
static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
{
struct rk322x_grf *grf;
@@ -328,6 +420,25 @@ static void rk3288_gmac_set_to_rgmii(struct
gmac_rockchip_platdata *pdata)
pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
}
+static void rk3328_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk3328_grf_regs *grf;
+ enum {
+ RK3328_RMII_MODE_MASK = BIT(9),
+ RK3328_RMII_MODE = BIT(9),
+
+ RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
+ RK3328_GMAC_PHY_INTF_SEL_RMII = BIT(6),
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] :
&grf->mac_con[1],
+ RK3328_RMII_MODE_MASK |
+ RK3328_GMAC_PHY_INTF_SEL_MASK,
+ RK3328_GMAC_PHY_INTF_SEL_RMII |
+ RK3328_RMII_MODE);
+}
+
static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
{
struct rk3328_grf_regs *grf;
@@ -551,7 +662,9 @@ const struct eth_ops gmac_rockchip_eth_ops = {
};
const struct rk_gmac_ops rk3228_gmac_ops = {
+ .fix_rmii_speed = rk3228_gmac_fix_rmii_speed,
.fix_rgmii_speed = rk3228_gmac_fix_rgmii_speed,
+ .set_to_rmii = rk3228_gmac_set_to_rmii,
.set_to_rgmii = rk3228_gmac_set_to_rgmii,
};
@@ -561,7 +674,9 @@ const struct rk_gmac_ops rk3288_gmac_ops = {
};
const struct rk_gmac_ops rk3328_gmac_ops = {
+ .fix_rmii_speed = rk3328_gmac_fix_rmii_speed,
.fix_rgmii_speed = rk3328_gmac_fix_rgmii_speed,
+ .set_to_rmii = rk3328_gmac_set_to_rmii,
.set_to_rgmii = rk3328_gmac_set_to_rgmii,
};
--
2.7.4
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