Re: [U-Boot] [PATCH 07/10 V4] EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0

2012/6/29 Rajeshwari Shinde : > MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz. > Adjust the divisor value to get 800MHz as needed by devices > like UART etc > > Signed-off-by: Hatim Ali > Signed-off-by: Rajeshwari Shinde > --- > Changes in V2: >        - None > Changes in V3: >        

[U-Boot] [PATCH 07/10 V4] EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0

MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz. Adjust the divisor value to get 800MHz as needed by devices like UART etc Signed-off-by: Hatim Ali Signed-off-by: Rajeshwari Shinde --- Changes in V2: - None Changes in V3: - Incorported review comments from Minkyu Kang. C