Re: [U-Boot] [PATCH 1/2] ARM: tegra124: Clear IDDQ when enabling PLLC

2015-09-10 Thread Thierry Reding
On Wed, Sep 09, 2015 at 08:37:34PM -0700, Stephen Warren wrote: > On 09/08/2015 02:38 AM, Thierry Reding wrote: > > From: Thierry Reding > > > > Enabling a PLL while IDDQ is high. The Linux kernel checks for this > > Is there some word missing in/at-the-end-of that first

Re: [U-Boot] [PATCH 1/2] ARM: tegra124: Clear IDDQ when enabling PLLC

2015-09-09 Thread Stephen Warren
On 09/08/2015 02:38 AM, Thierry Reding wrote: > From: Thierry Reding > > Enabling a PLL while IDDQ is high. The Linux kernel checks for this Is there some word missing in/at-the-end-of that first sentence? It doesn't seem complete. > condition and warns about it verbosely,

Re: [U-Boot] [PATCH 1/2] ARM: tegra124: Clear IDDQ when enabling PLLC

2015-09-09 Thread Nicolas Chauvet
Tested-by: Nicolas Chauvet Test-HW: jetson-tk1 Fix the issue on recent kernel Nicolas (kwizart) 2015-09-08 11:38 GMT+02:00 Thierry Reding : > From: Thierry Reding > > Enabling a PLL while IDDQ is high. The Linux kernel checks

[U-Boot] [PATCH 1/2] ARM: tegra124: Clear IDDQ when enabling PLLC

2015-09-08 Thread Thierry Reding
From: Thierry Reding Enabling a PLL while IDDQ is high. The Linux kernel checks for this condition and warns about it verbosely, so while this seems to work fine, fix it up according to the programming guidelines provided in the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and