Re: [U-Boot] [PATCH 1/2] arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

2016-10-29 Thread Keerthy
On Friday 28 October 2016 06:42 PM, Tom Rini wrote: On Fri, Oct 28, 2016 at 12:01:43PM +0530, Keerthy wrote: While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mar

Re: [U-Boot] [PATCH 1/2] arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

2016-10-28 Thread Tom Rini
On Fri, Oct 28, 2016 at 12:01:43PM +0530, Keerthy wrote: > While we setup the mmu initially we mark set_section_dcache with > DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro > is rightly defined with TTB_SECT_XN_MASK set so as to mark all the > 4GB XN. In case of LPAE mode XN(Execut

Re: [U-Boot] [PATCH 1/2] arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

2016-10-28 Thread Alexander Graf
On 28/10/2016 08:31, Keerthy wrote: > While we setup the mmu initially we mark set_section_dcache with > DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro > is rightly defined with TTB_SECT_XN_MASK set so as to mark all the > 4GB XN. In case of LPAE mode XN(Execute-never) bit is not

[U-Boot] [PATCH 1/2] arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

2016-10-27 Thread Keerthy
While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set