Hi Christian,
Le 18/02/2012 19:51, Christian Riesch a écrit :
Hi Albert,
On Saturday, February 18, 2012, Albert ARIBAUD
wrote:
Le 14/01/2012 15:02, Sughosh Ganu a écrit :
The current implementation invalidates the cache instead of flushing
it. This causes problems on platforms where the spl/
Hi Albert,
On Saturday, February 18, 2012, Albert ARIBAUD
wrote:
> Le 14/01/2012 15:02, Sughosh Ganu a écrit :
>>
>> The current implementation invalidates the cache instead of flushing
>> it. This causes problems on platforms where the spl/u-boot is already
>> loaded to the RAM, with caches enab
Hi Sughosh
Le 14/01/2012 10:21, Sughosh Ganu a écrit :
hi Albert,
On Sat Jan 14, 2012 at 10:02:16AM +0100, Albert ARIBAUD wrote:
/*
-* disable MMU stuff and caches
+* disable MMU and D cache, and enable I cache.
*/
mrc p15, 0, r0, c1, c0, 0
-
hi Albert,
On Sat Jan 14, 2012 at 10:02:16AM +0100, Albert ARIBAUD wrote:
> > /*
> >- * disable MMU stuff and caches
> >+ * disable MMU and D cache, and enable I cache.
> > */
> > mrc p15, 0, r0, c1, c0, 0
> >-bic r0, r0, #0x2300 /* clear bits 13, 9:8 (-
Hi Sughosh,
Le 14/01/2012 08:49, Sughosh Ganu a écrit :
The current implementation invalidates the cache instead of flushing
it. This causes problems on platforms where the spl/u-boot is already
loaded to the RAM, with caches enabled by a first stage bootloader.
The V bit of the cp15's control
The current implementation invalidates the cache instead of flushing
it. This causes problems on platforms where the spl/u-boot is already
loaded to the RAM, with caches enabled by a first stage bootloader.
The V bit of the cp15's control register c1 is set to the value of
VINITHI on reset. Do not
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