Re: [U-Boot] [PATCH 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-09-20 Thread Marek Vasut
On 09/20/2016 07:50 AM, Chin Liang See wrote: > On Mon, 2016-09-19 at 20:54 +0200, Marek Vasut wrote: >> On 09/19/2016 12:11 PM, Chin Liang See wrote: >>> On Mon, 2016-09-19 at 16:22 +0200, Marek Vasut wrote: On 09/15/2016 09:26 AM, Chin Liang See wrote: > To enable configuration of sdr.ct

Re: [U-Boot] [PATCH 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-09-19 Thread Chin Liang See
On Mon, 2016-09-19 at 20:54 +0200, Marek Vasut wrote: > On 09/19/2016 12:11 PM, Chin Liang See wrote: > > On Mon, 2016-09-19 at 16:22 +0200, Marek Vasut wrote: > > > On 09/15/2016 09:26 AM, Chin Liang See wrote: > > > > To enable configuration of sdr.ctrlcfg.extratime1 register > > > > which > > >

Re: [U-Boot] [PATCH 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-09-19 Thread Marek Vasut
On 09/19/2016 08:54 PM, Marek Vasut wrote: > On 09/19/2016 12:11 PM, Chin Liang See wrote: >> On Mon, 2016-09-19 at 16:22 +0200, Marek Vasut wrote: >>> On 09/15/2016 09:26 AM, Chin Liang See wrote: To enable configuration of sdr.ctrlcfg.extratime1 register which enable extra clocks f

Re: [U-Boot] [PATCH 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-09-19 Thread Marek Vasut
On 09/19/2016 12:11 PM, Chin Liang See wrote: > On Mon, 2016-09-19 at 16:22 +0200, Marek Vasut wrote: >> On 09/15/2016 09:26 AM, Chin Liang See wrote: >>> To enable configuration of sdr.ctrlcfg.extratime1 register which >>> enable >>> extra clocks for read to write command timing. This is critical

Re: [U-Boot] [PATCH 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-09-19 Thread Chin Liang See
On Mon, 2016-09-19 at 16:22 +0200, Marek Vasut wrote: > On 09/15/2016 09:26 AM, Chin Liang See wrote: > > To enable configuration of sdr.ctrlcfg.extratime1 register which > > enable > > extra clocks for read to write command timing. This is critical to > > ensure successful LPDDR2 interface > > >

Re: [U-Boot] [PATCH 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-09-19 Thread Marek Vasut
On 09/15/2016 09:26 AM, Chin Liang See wrote: > To enable configuration of sdr.ctrlcfg.extratime1 register which enable > extra clocks for read to write command timing. This is critical to > ensure successful LPDDR2 interface > > Signed-off-by: Chin Liang See > --- > arch/arm/mach-socfpga/includ

[U-Boot] [PATCH 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters

2016-09-19 Thread Chin Liang See
To enable configuration of sdr.ctrlcfg.extratime1 register which enable extra clocks for read to write command timing. This is critical to ensure successful LPDDR2 interface Signed-off-by: Chin Liang See --- arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++- arch/arm/mach-socfpga/qts-filte