On Wednesday 06 November 2013 06:18 PM, Vaibhav Bedia wrote:
> On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla wrote:
>> Updating the Multiplier and Dividers values for all DPLLs for EPOS EVM.
>> Following are the DPLL locking frequencies at OPP NOM:
>> MPU locks at 600MHz
>> Core locks at 1000MHz
>
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla wrote:
> Updating the Multiplier and Dividers values for all DPLLs for EPOS EVM.
> Following are the DPLL locking frequencies at OPP NOM:
> MPU locks at 600MHz
> Core locks at 1000MHz
> Per locks at 960MHz
> DDR locks at 266MHz
>
Why is this not readi
Updating the Multiplier and Dividers values for all DPLLs for EPOS EVM.
Following are the DPLL locking frequencies at OPP NOM:
MPU locks at 600MHz
Core locks at 1000MHz
Per locks at 960MHz
DDR locks at 266MHz
Signed-off-by: Lokesh Vutla
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arch/arm/cpu/armv7/am33xx/clock.c| 12 +++
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