According to Jens disabling the on-die-termination should set bit 5,
not bit 1 in the respective register. Fix this.
Reported-by: Jens Kuske <jensku...@gmail.com>
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
arch/arm/mach-sunxi/dram_sun8i_h3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c
b/arch/arm/mach-sunxi/dram_sun8i_h3.c
index 2dc2071..3d569fc 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
@@ -385,7 +385,7 @@ static int mctl_channel_init(struct dram_para *para)
clrsetbits_le32(&mctl_ctl->dx[i].gcr, (0x3 << 4) |
(0x1 << 1) | (0x3 << 2) | (0x3 << 12) |
(0x3 << 14),
- IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x2);
+ IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x20);
/* AC PDR should always ON */
setbits_le32(&mctl_ctl->aciocr, 0x1 << 1);
--
2.8.2
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