Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
code uses it as hosekeeping area.
3. For Secure boot, CPC is configured as SRAM and used as house
keeping area. This configuration is to be disabled once in uboot.
Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
As a result cache invalidation function was getting skipped in
case CPC is configured as SRAM.This was causing random crashes.
Signed-off-by: Ruchika Gupta <ruchika.gu...@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.ban...@freescale.com>
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 28 +++++++++++++++++++++++-----
arch/powerpc/cpu/mpc85xx/start.S | 3 ++-
arch/powerpc/include/asm/fsl_secure_boot.h | 6 ++++++
boards.cfg | 1 +
4 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index b31efb7..de1116b 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -125,17 +125,15 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
#endif
#ifdef CONFIG_SYS_FSL_CPC
-static void enable_cpc(void)
+
+#ifdef CONFIG_RAMBOOT_PBL || defined(CONFIG_SECURE_HKAREA_CPC)
+static void disable_cpc_sram(void)
{
int i;
- u32 size = 0;
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
- u32 cpccfg0 = in_be32(&cpc->cpccfg0);
- size += CPC_CFG0_SZ_K(cpccfg0);
-#ifdef CONFIG_RAMBOOT_PBL
if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
/* find and disable LAW of SRAM */
struct law_entry law =
find_law(CONFIG_SYS_INIT_L3_ADDR);
@@ -150,8 +148,21 @@ static void enable_cpc(void)
out_be32(&cpc->cpccsr0, 0);
out_be32(&cpc->cpcsrcr0, 0);
}
+ }
+}
#endif
+static void enable_cpc(void)
+{
+ int i;
+ u32 size = 0;
+
+ cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+
+ for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
+ u32 cpccfg0 = in_be32(&cpc->cpccfg0);
+ size += CPC_CFG0_SZ_K(cpccfg0);
+
#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
#endif
@@ -250,6 +261,10 @@ void cpu_init_f (void)
law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
if (law.index != -1)
disable_law(law.index);
+
+#if defined(CONFIG_SECURE_HKAREA_CPC)
+ disable_cpc_sram();
+#endif
#endif
#ifdef CONFIG_CPM2
@@ -550,6 +565,9 @@ skip_l2:
puts("disabled\n");
#endif
+#if defined(CONFIG_RAMBOOT_PBL)
+ disable_cpc_sram();
+#endif
enable_cpc();
#ifndef CONFIG_SYS_FSL_NO_SERDES
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index db84d10..5440bf5 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -117,7 +117,8 @@ _start_e500:
#endif
-#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \
+ !defined(CONFIG_E6500)
/* ISBC uses L2 as stack.
* Disable L2 cache here so that u-boot can enable it later
* as part of it's normal flow
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h
b/arch/powerpc/include/asm/fsl_secure_boot.h
index 4c7f0b1..db124df 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -15,5 +15,11 @@
#endif
#define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
+#if CONFIG_SYS_FSL_ISBC_VER > 1
+#define CONFIG_SECURE_HKAREA_CPC
+#undef CONFIG_SYS_INIT_L3_ADDR
+#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
+#endif
+
#endif
#endif
diff --git a/boards.cfg b/boards.cfg
index 928e222..1d6a14c 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -780,6 +780,7 @@ Active powerpc mpc85xx - freescale
b4860qds
Active powerpc mpc85xx - freescale b4860qds
B4420QDS_NAND
B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
-
Active powerpc mpc85xx - freescale b4860qds
B4420QDS_SPIFLASH
B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
-
Active powerpc mpc85xx - freescale b4860qds
B4860QDS B4860QDS:PPC_B4860
-
+Active powerpc mpc85xx - freescale b4860qds
B4860QDS_SECURE_BOOT B4860QDS:PPC_B4860,SECURE_BOOT
Aneesh Bansal <aneesh.ban...@freescale.com>
Active powerpc mpc85xx - freescale b4860qds
B4860QDS_NAND
B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
-
Active powerpc mpc85xx - freescale b4860qds
B4860QDS_SPIFLASH
B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
-
Active powerpc mpc85xx - freescale b4860qds
B4860QDS_SRIO_PCIE_BOOT
B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
-
--
1.8.1.4
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