On the DA830, UART2's clock is derived from PLL controller 0 output 2.
On the DA850, it is in the ASYNC3 group, and may be switched between PLL
controller 0 or 1. Fix the definition of the ID to match.
Signed-off-by: Laurence Withers <lwith...@guralp.com>
Cc: Prabhakar Lad <prabhakar.cse...@gmail.com>
---
arch/arm/include/asm/arch-davinci/hardware.h | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index dac43bb..0fce940 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -466,7 +466,6 @@ enum davinci_clk_ids {
DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4,
DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2,
DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2,
- DAVINCI_UART2_CLKID = DAVINCI_PLL0_SYSCLK2,
/* special clock ID - output of PLL multiplier */
DAVINCI_PLLM_CLKID = 0x0FF,
@@ -478,6 +477,9 @@ enum davinci_clk_ids {
DAVINCI_AUXCLK_CLKID = 0x101,
};
+#define DAVINCI_UART2_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
+ : get_async3_src())
+
#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
: get_async3_src())
--
1.7.2.5
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