Signed-off-by: Stefan Roese <s...@denx.de> Cc: Chin Liang See <cl...@altera.com> Cc: Dinh Nguyen <dingu...@altera.com> Cc: Vince Bridgers <vbrid...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Pavel Machek <pa...@denx.de> Cc: Michael Trimarchi <mich...@amarulasolutions.com> Cc: Jagannadha Sutradharudu Teki <jagannadh.t...@gmail.com> --- include/configs/socfpga_cyclone5_common.h | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)
diff --git a/include/configs/socfpga_cyclone5_common.h b/include/configs/socfpga_cyclone5_common.h index 3f8f91f..d183510 100644 --- a/include/configs/socfpga_cyclone5_common.h +++ b/include/configs/socfpga_cyclone5_common.h @@ -142,6 +142,37 @@ #endif /* + * QSPI support + */ +#ifdef CONFIG_CMD_SF +#define CONFIG_CADENCE_QSPI +#define CONFIG_CQSPI_BASE (SOCFPGA_QSPI_ADDRESS) +#define CONFIG_CQSPI_AHB_BASE (SOCFPGA_QSPIDATA_ADDRESS) +#define CONFIG_SPI_FLASH /* SPI flash subsystem */ +#define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */ +#define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */ +#define CONFIG_SPI_FLASH_MTD +/* Flash device info */ +#define CONFIG_SF_DEFAULT_SPEED (50000000) +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 +#define CONFIG_SPI_FLASH_QUAD (1) +/* QSPI reference clock */ +#ifndef __ASSEMBLY__ +unsigned int cm_get_qspi_controller_clk_hz(void); +#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() +#endif +/* QSPI page size and block size */ +#define CONFIG_CQSPI_PAGE_SIZE (256) +#define CONFIG_CQSPI_BLOCK_SIZE (16) +/* QSPI Delay timing */ +#define CONFIG_CQSPI_TSHSL_NS (200) +#define CONFIG_CQSPI_TSD2D_NS (255) +#define CONFIG_CQSPI_TCHSH_NS (20) +#define CONFIG_CQSPI_TSLCH_NS (20) +#define CONFIG_CQSPI_DECODER (0) +#endif /* CONFIG_CMD_SF */ + +/* * Serial Driver */ #define CONFIG_SYS_NS16550 -- 2.1.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
