The UART0 and UART1 resets are missing from DT, so the reset manager cannot control them. Add the missing DT reset entries.
Signed-off-by: Marek Vasut <ma...@denx.de> Cc: Chin Liang See <chin.liang....@intel.com> Cc: Dinh Nguyen <dingu...@kernel.org> Cc: Ley Foon Tan <ley.foon....@intel.com> --- arch/arm/dts/socfpga_arria10.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi index 51b31dc2b5..aafcfe9ce4 100644 --- a/arch/arm/dts/socfpga_arria10.dtsi +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -797,6 +797,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&l4_sp_clk>; + resets = <&rst UART0_RESET>; status = "disabled"; }; @@ -807,6 +808,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&l4_sp_clk>; + resets = <&rst UART1_RESET>; status = "disabled"; }; -- 2.16.2 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot