Adds base addresses of various IPs and controllers required for
Exynos5420.
Signed-off-by: Rajeshwari S Shinde <rajeshwar...@samsung.com>
Signed-off-by: Akshay Saraswat <aksha...@samsung.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- Added base address for TZPC.
Changes in V5:
- None
Chnages in V6:
- Rebased on latest samsung mainline branch.
Changes in V7:
- Corrected the comments
arch/arm/include/asm/arch-exynos/cpu.h | 47 +++++++++++++++++++++++++++++++++-
1 file changed, 46 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h
b/arch/arm/include/asm/arch-exynos/cpu.h
index 4b67191..a465e6d 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -88,7 +88,7 @@
#define EXYNOS4X12_DMC_PHY_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
-/* EXYNOS5 Common*/
+/* EXYNOS5 */
#define EXYNOS5_I2C_SPACING 0x10000
#define EXYNOS5_AUDIOSS_BASE 0x03810000
@@ -124,6 +124,44 @@
#define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE
+/* EXYNOS5420 */
+#define EXYNOS5420_AUDIOSS_BASE 0x03810000
+#define EXYNOS5420_GPIO_PART5_BASE 0x03860000
+#define EXYNOS5420_PRO_ID 0x10000000
+#define EXYNOS5420_CLOCK_BASE 0x10010000
+#define EXYNOS5420_POWER_BASE 0x10040000
+#define EXYNOS5420_SWRESET 0x10040400
+#define EXYNOS5420_SYSREG_BASE 0x10050000
+#define EXYNOS5420_TZPC_BASE 0x100E0000
+#define EXYNOS5420_WATCHDOG_BASE 0x101D0000
+#define EXYNOS5420_ACE_SFR_BASE 0x10830000
+#define EXYNOS5420_DMC_PHY_BASE 0x10C00000
+#define EXYNOS5420_DMC_CTRL_BASE 0x10C20000
+#define EXYNOS5420_DMC_TZASC0_BASE 0x10D40000
+#define EXYNOS5420_DMC_TZASC1_BASE 0x10D50000
+#define EXYNOS5420_USB_HOST_EHCI_BASE 0x12110000
+#define EXYNOS5420_MMC_BASE 0x12200000
+#define EXYNOS5420_SROMC_BASE 0x12250000
+#define EXYNOS5420_UART_BASE 0x12C00000
+#define EXYNOS5420_I2C_BASE 0x12C60000
+#define EXYNOS5420_I2C_8910_BASE 0x12E00000
+#define EXYNOS5420_SPI_BASE 0x12D20000
+#define EXYNOS5420_I2S_BASE 0x12D60000
+#define EXYNOS5420_PWMTIMER_BASE 0x12DD0000
+#define EXYNOS5420_SPI_ISP_BASE 0x131A0000
+#define EXYNOS5420_GPIO_PART2_BASE 0x13400000
+#define EXYNOS5420_GPIO_PART3_BASE 0x13410000
+#define EXYNOS5420_GPIO_PART4_BASE 0x14000000
+#define EXYNOS5420_GPIO_PART1_BASE 0x14010000
+#define EXYNOS5420_MIPI_DSIM_BASE 0x14500000
+#define EXYNOS5420_DP_BASE 0x145B0000
+
+#define EXYNOS5420_USBPHY_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_USBOTG_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_FIMD_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_ADC_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS5420_MODEM_BASE DEVICE_NOT_AVAILABLE
+
#ifndef __ASSEMBLY__
#include <asm/io.h>
/* CPU detection macros */
@@ -157,6 +195,10 @@ static inline void s5p_set_cpu_id(void)
/* Exynos5250 */
s5p_cpu_id = 0x5250;
break;
+ case 0x420:
+ /* Exynos5420 */
+ s5p_cpu_id = 0x5420;
+ break;
}
}
@@ -184,6 +226,7 @@ static inline int __attribute__((no_instrument_function)) \
IS_EXYNOS_TYPE(exynos4210, 0x4210)
IS_EXYNOS_TYPE(exynos4412, 0x4412)
IS_EXYNOS_TYPE(exynos5250, 0x5250)
+IS_EXYNOS_TYPE(exynos5420, 0x5420)
#define SAMSUNG_BASE(device, base) \
static inline unsigned int __attribute__((no_instrument_function)) \
@@ -194,6 +237,8 @@ static inline unsigned int
__attribute__((no_instrument_function)) \
return EXYNOS4X12_##base; \
return EXYNOS4_##base; \
} else if (cpu_is_exynos5()) { \
+ if (proid_is_exynos5420()) \
+ return EXYNOS5420_##base; \
return EXYNOS5_##base; \
} \
return 0; \
--
1.7.12.4
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