README states that CONFIG_SYS_SDRAM_BASE should the physical base
address of SDRAM, whilst up until now various pieces of generic code
have presumed that it can be directly accessed by the CPU & MIPS has
provided a virtual address for CONFIG_SYS_SDRAM_BASE. Other generic code
expects CONFIG_SYS_SDRAM_BASE to be a physical address, which makes the
inconsistency a mess.
Now that the preceding patches have prepared us to handle using a
physical CONFIG_SYS_SDRAM_BASE, clean up the inconsistency for the
remaining MIPS boards by providing a physical CONFIG_SYS_SDRAM_BASE.
None of these boards use CONFIG_SYS_SDRAM_BASE in their code, so they're
handled together.
This has only been build-tested, feedback welcome.
Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierz...@gmail.com>
Cc: Marek Vasut <ma...@denx.de>
Cc: Purna Chandra Mandal <purna.man...@microchip.com>
Cc: Wills Wang <wills.w...@live.com>
---
include/configs/ap121.h | 2 +-
include/configs/ap143.h | 2 +-
include/configs/dbau1x00.h | 2 +-
include/configs/pb1x00.h | 2 +-
include/configs/pic32mzdask.h | 2 +-
include/configs/qemu-mips.h | 2 +-
include/configs/qemu-mips64.h | 2 +-
include/configs/tplink_wdr4300.h | 2 +-
include/configs/vct.h | 2 +-
9 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/include/configs/ap121.h b/include/configs/ap121.h
index bf5746f..63e0015 100644
--- a/include/configs/ap121.h
+++ b/include/configs/ap121.h
@@ -20,7 +20,7 @@
#define CONFIG_SYS_MALLOC_LEN 0x40000
#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_SDRAM_BASE 0x0
#define CONFIG_SYS_LOAD_ADDR 0x81000000
#define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/ap143.h b/include/configs/ap143.h
index 5d7e49e..a8721e6 100644
--- a/include/configs/ap143.h
+++ b/include/configs/ap143.h
@@ -20,7 +20,7 @@
#define CONFIG_SYS_MALLOC_LEN 0x40000
#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_SDRAM_BASE 0x0
#define CONFIG_SYS_LOAD_ADDR 0x81000000
#define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index dbd2bb3..b369d71 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -105,7 +105,7 @@
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
+#define CONFIG_SYS_SDRAM_BASE 0x0 /* Cached addr */
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load
address */
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index fb5278f..8ef334f 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -61,7 +61,7 @@
#define CONFIG_SYS_MIPS_TIMER_FREQ 396000000
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
+#define CONFIG_SYS_SDRAM_BASE 0x0 /* Cached addr */
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load
address */
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 49c98d8..5b80b46 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -35,7 +35,7 @@
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1)
/* SDRAM Configuration (for final code, data, stack, heap) */
-#define CONFIG_SYS_SDRAM_BASE 0x88000000
+#define CONFIG_SYS_SDRAM_BASE 0x08000000
#define CONFIG_SYS_MALLOC_LEN (256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN (4 << 10)
#define CONFIG_STACKSIZE (4 << 10) /* regular stack */
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index 546c508..7e839a8 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -94,7 +94,7 @@
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
/* Cached addr */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_SDRAM_BASE 0x0
/* default load address */
#define CONFIG_SYS_LOAD_ADDR 0x81000000
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
index 6cab719..18e3294 100644
--- a/include/configs/qemu-mips64.h
+++ b/include/configs/qemu-mips64.h
@@ -94,7 +94,7 @@
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
/* Cached addr */
-#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
+#define CONFIG_SYS_SDRAM_BASE 0x0
/* default load address */
#define CONFIG_SYS_LOAD_ADDR 0xffffffff81000000
diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h
index 7bf8e4c..5a6a0d4 100644
--- a/include/configs/tplink_wdr4300.h
+++ b/include/configs/tplink_wdr4300.h
@@ -20,7 +20,7 @@
#define CONFIG_SYS_MALLOC_LEN 0x40000
#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
-#define CONFIG_SYS_SDRAM_BASE 0xa0000000
+#define CONFIG_SYS_SDRAM_BASE 0x0
#define CONFIG_SYS_LOAD_ADDR 0xa1000000
#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
diff --git a/include/configs/vct.h b/include/configs/vct.h
index f2e0e5c..3e50619 100644
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -63,7 +63,7 @@
/*
* SDRAM
*/
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_SDRAM_BASE 0x0
#define CONFIG_SYS_MBYTES_SDRAM 128
#define CONFIG_SYS_MEMTEST_START 0x80200000
#define CONFIG_SYS_MEMTEST_END 0x80400000
--
2.10.0
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